330 lines
9.0 KiB
C
330 lines
9.0 KiB
C
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <check.h>
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#include "../p4-interp.h"
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/* check decoding and execution of the HALT instruction */
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START_TEST (D_func_decode_halt)
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{
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y86_t cpu;
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA = 0;
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y86_reg_t valE = 0;
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memset (&inst, 0, sizeof (inst));
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inst.icode = HALT;
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memset (&cpu, 0, sizeof (cpu));
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cpu.stat = AOK;
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == 0 || valE != 0);
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ck_assert (cpu.stat == HLT);
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}
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END_TEST
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/* check decoding and execution of the NOP instruction */
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START_TEST (D_func_decode_nop)
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{
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y86_t cpu;
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA = 0;
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y86_reg_t valE = 0;
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memset (&inst, 0, sizeof (inst));
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inst.icode = NOP;
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memset (&cpu, 0, sizeof (cpu));
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cpu.stat = AOK;
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == 0 || valE != 0);
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ck_assert (cpu.stat == AOK);
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}
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END_TEST
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/* check memory, writeback, and PC update of the HALT instruction */
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START_TEST (D_func_memory_halt)
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{
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y86_t cpu;
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byte_t *memory = malloc (MEMSIZE);
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA;
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y86_reg_t valE;
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memset (&cpu, 0, sizeof (cpu));
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memset (memory, 0, MEMSIZE);
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memset (&inst, 0, sizeof (inst));
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cpu.stat = AOK;
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valA = valE = 0;
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inst.icode = HALT;
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inst.valP = rand() % MEMSIZE;
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memory_wb_pc (&cpu, &inst, memory, cnd, valA, valE);
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ck_assert (cpu.pc == inst.valP);
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}
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END_TEST
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/* check memory, writeback, and PC update of the NOP instruction */
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START_TEST (D_func_memory_nop)
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{
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y86_t cpu;
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byte_t *memory = malloc (MEMSIZE);
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA;
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y86_reg_t valE;
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memset (&cpu, 0, sizeof (cpu));
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memset (memory, 0, MEMSIZE);
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memset (&inst, 0, sizeof (inst));
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cpu.stat = AOK;
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valA = valE = 0;
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inst.icode = NOP;
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inst.valP = rand() % MEMSIZE;
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memory_wb_pc (&cpu, &inst, memory, cnd, valA, valE);
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ck_assert (cpu.pc == inst.valP);
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}
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END_TEST
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/* check for null-pointer handling */
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START_TEST (D_error_decode_NULL_cnd_valA)
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{
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y86_t cpu;
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y86_inst_t inst;
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y86_reg_t valE = 0;
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memset (&inst, 0, sizeof (inst));
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memset (&cpu, 0, sizeof (cpu));
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cpu.stat = AOK;
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inst.icode = NOP;
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valE = decode_execute (&cpu, &inst, NULL, NULL);
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ck_assert (valE == 0 || valE != 0);
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ck_assert (cpu.stat == INS);
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}
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END_TEST
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/* helper function: extract the given register value from a CPU state */
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static y86_reg_t _check_get_reg (y86_t *cpu, y86_regnum_t num)
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{
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return cpu->reg[num];
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}
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/* check decoding and execution of the IRMOVQ instruction */
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START_TEST (C_func_decode_irmovq)
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{
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y86_t cpu;
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA = 0;
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y86_reg_t valE = 0;
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/* assemble test instruction and initial CPU state */
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memset (&inst, 0, sizeof (inst));
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inst.icode = IRMOVQ;
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memset (&cpu, 0, sizeof (cpu));
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cpu.stat = AOK;
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inst.valC.v = 0 + rand();
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inst.rb = (y86_regnum_t)(rand() % NOREG); /* random register */
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/* test: load a positive value */
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == (y86_reg_t)inst.valC.v);
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ck_assert (cpu.sf == 0);
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ck_assert (cpu.zf == 0);
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ck_assert (_check_get_reg (&cpu, inst.rb) == 0);
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/* test: load a negative value */
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inst.valC.v = -inst.valC.v;
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == (y86_reg_t)inst.valC.v);
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ck_assert (cpu.sf == 0);
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ck_assert (cpu.zf == 0);
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ck_assert (_check_get_reg (&cpu, inst.rb) == 0);
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/* test: load a zero value */
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inst.valC.v = 0;
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == (y86_reg_t)inst.valC.v);
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ck_assert (cpu.sf == 0);
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ck_assert (cpu.zf == 0);
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ck_assert (_check_get_reg (&cpu, inst.rb) == 0);
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}
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END_TEST
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/* helper function: set the given register value in a CPU state */
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static void _check_set_reg (y86_t *cpu, y86_regnum_t num, y86_reg_t val)
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{
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cpu->reg[num] = val;
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}
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/* check decoding and execution of the OPq instructions (no CC testing) */
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START_TEST (C_func_decode_opq)
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{
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y86_t cpu;
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA = 0;
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y86_reg_t valE = 0;
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y86_reg_t expected_valE = 0;
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y86_reg_t regs[NOREG];
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uint8_t i = 0;
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memset (&inst, 0, sizeof (inst));
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inst.icode = OPQ;
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memset (&cpu, 0, sizeof (cpu));
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cpu.stat = AOK;
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for (i = RAX; i < NOREG; i++)
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{
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/* set registers to random values */
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regs[i] = (((int64_t)rand()) << 32) | rand();
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_check_set_reg (&cpu, i, regs[i]);
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}
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/* addition */
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inst.ra = (y86_regnum_t)(rand() % NOREG);
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inst.rb = (y86_regnum_t)(rand() % NOREG);
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inst.ifun.op = ADD;
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expected_valE = _check_get_reg (&cpu, inst.ra) + _check_get_reg (&cpu, inst.rb);
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == expected_valE);
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ck_assert (regs[inst.ra] == _check_get_reg (&cpu, inst.ra));
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ck_assert (regs[inst.rb] == _check_get_reg (&cpu, inst.rb));
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/* subtraction */
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inst.ra = (y86_regnum_t)(rand() % NOREG);
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inst.rb = (y86_regnum_t)(rand() % NOREG);
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inst.ifun.op = SUB;
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expected_valE = _check_get_reg (&cpu, inst.rb) - _check_get_reg (&cpu, inst.ra);
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == expected_valE);
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ck_assert (regs[inst.ra] == _check_get_reg (&cpu, inst.ra));
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ck_assert (regs[inst.rb] == _check_get_reg (&cpu, inst.rb));
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/* bitwise AND */
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inst.ra = (y86_regnum_t)(rand() % NOREG);
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inst.rb = (y86_regnum_t)(rand() % NOREG);
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inst.ifun.op = AND;
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expected_valE = _check_get_reg (&cpu, inst.ra) & _check_get_reg (&cpu, inst.rb);
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == expected_valE);
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ck_assert (regs[inst.ra] == _check_get_reg (&cpu, inst.ra));
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ck_assert (regs[inst.rb] == _check_get_reg (&cpu, inst.rb));
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/* bitwise XOR */
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inst.ra = (y86_regnum_t)(rand() % NOREG);
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inst.rb = (y86_regnum_t)(rand() % NOREG);
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inst.ifun.op = XOR;
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expected_valE = _check_get_reg (&cpu, inst.ra) ^ _check_get_reg (&cpu, inst.rb);
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == expected_valE);
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ck_assert (regs[inst.ra] == _check_get_reg (&cpu, inst.ra));
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ck_assert (regs[inst.rb] == _check_get_reg (&cpu, inst.rb));
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}
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END_TEST
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/* check handling of invalid OPq instruction */
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START_TEST (C_error_decode_invalid_opq)
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{
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y86_t cpu;
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA = 0;
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y86_reg_t valE = 0;
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memset (&inst, 0, sizeof (inst));
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memset (&cpu, 0, sizeof (cpu));
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cpu.stat = AOK;
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inst.icode = OPQ;
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inst.ifun.op = BADOP;
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valE = decode_execute (&cpu, &inst, &cnd, &valA);
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ck_assert (valE == 0 || valE != 0);
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ck_assert (cpu.stat == INS);
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}
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END_TEST
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/* check memory, writeback, and PC update of the IRMOVQ instruction */
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START_TEST (C_func_memory_irmovq)
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{
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y86_t cpu;
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byte_t *memory = malloc (MEMSIZE);
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA;
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y86_reg_t valE;
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for (y86_regnum_t reg = RAX; reg < NOREG; reg++) {
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valA = 0;
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memset (&cpu, 0, sizeof (cpu));
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memset (memory, 0, MEMSIZE);
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memset (&inst, 0, sizeof (inst));
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cpu.stat = AOK;
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inst.icode = IRMOVQ;
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inst.rb = reg;
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inst.valP = rand() % MEMSIZE;
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valE = rand();
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memory_wb_pc (&cpu, &inst, memory, cnd, valA, valE);
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ck_assert (cpu.stat == AOK);
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ck_assert (cpu.reg[reg] == valE);
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ck_assert (cpu.pc == inst.valP);
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}
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}
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END_TEST
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/* check memory, writeback, and PC update of the OPQ instruction */
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START_TEST (C_func_memory_opq)
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{
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y86_t cpu;
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byte_t *memory = malloc (MEMSIZE);
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y86_inst_t inst;
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bool cnd = false;
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y86_reg_t valA;
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y86_reg_t valE;
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for (y86_regnum_t reg = RAX; reg < NOREG; reg++) {
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valA = 0;
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memset (&cpu, 0, sizeof (cpu));
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memset (memory, 0, MEMSIZE);
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memset (&inst, 0, sizeof (inst));
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cpu.stat = AOK;
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inst.icode = OPQ;
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inst.rb = reg;
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inst.valP = rand() % MEMSIZE;
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valE = rand();
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memory_wb_pc (&cpu, &inst, memory, cnd, valA, valE);
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ck_assert (cpu.stat == AOK);
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ck_assert (cpu.reg[reg] == valE);
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ck_assert (cpu.pc == inst.valP);
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}
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}
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END_TEST
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void public_tests (Suite *s)
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{
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TCase *tc_public = tcase_create ("Public");
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tcase_add_test (tc_public, D_func_decode_halt);
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tcase_add_test (tc_public, D_func_decode_nop);
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tcase_add_test (tc_public, D_func_memory_halt);
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tcase_add_test (tc_public, D_func_memory_nop);
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tcase_add_test (tc_public, D_error_decode_NULL_cnd_valA);
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tcase_add_test (tc_public, C_func_decode_irmovq);
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tcase_add_test (tc_public, C_func_decode_opq);
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tcase_add_test (tc_public, C_func_memory_irmovq);
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tcase_add_test (tc_public, C_func_memory_opq);
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tcase_add_test (tc_public, C_error_decode_invalid_opq);
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suite_add_tcase (s, tc_public);
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}
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